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august 2010 doc id 13296 rev 12 1/40 1 stlm75 digital temperature sensor and thermal watchdog features measures temperatures from ?55c to +125c (?67f to +257f) ? 0.5 c (typ) accuracy ? 2 c (max) accuracy from ? 25c to +100 c low operating current: 125 a (typ) no external components required 2-wire i 2 c/smbus-compatible serial interface ? supports bus time-out feature ? selectable bus address allows connection of up to eight devices on the bus wide power supply range-operating voltage range: 2.7 v to 5.5 v conversion time is 150 ms (max) programmable temperature threshold and hysteresis set points pin- and software-compatible with lm75 (drop- in replacement) power-up defaults permit standalone operation as a thermostat shutdown mode to minimize power consumption output pin (open drain) can be configured for interrupt or comparator/thermostat mode (dual purpose event pin) packages: ?so8 ? msop8 (tssop8) so8 msop8 (tssop8) www.st.com
contents stlm75 2/40 doc id 13296 rev 12 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 temperature sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 sda (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 os /int (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.4 gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.5 a2, a1, a0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 thermal alarm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 fault tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 bus timeout feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 registers and register set formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 command/pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.3 temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.4 overlimit temperature register (t os ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.5 hysteresis temperature register (t hys ) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 power-up default conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
stlm75 contents doc id 13296 rev 12 3/40 3.4.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 typical operating char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables stlm75 4/40 doc id 13296 rev 12 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. fault tolerance setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. relationship between temperature and digital output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. command/pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. register pointers selection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 6. configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. t os and t hys register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. stlm75 serial bus slave addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. so8 ? 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 33 table 15. msop8 (tssop8) ? 8-lead, thin shrink small outline (3 mm x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. carrier tape dimensions for so8 and msop8 (tssop8) packages . . . . . . . . . . . . . . . . . 35 table 17. reel dimensions for 12 mm carrier tape - so8 and msop8 (tssop8) packages . . . . . . 36 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
stlm75 list of figures doc id 13296 rev 12 5/40 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. connections (so8 and msop8/tssop8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. typical 2-wire interface connections diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. os output temperature response diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. typical 2-byte read from preset pointer location (e.g. temp - t os , t hys ) . . . . . . . . . . . . 24 figure 10. typical pointer set followed by an immediate read for 2-byte register (e.g. temp). . . . . . 24 figure 11. typical 1-byte read from the configuration register with preset pointer . . . . . . . . . . . . . . 24 figure 12. typical pointer set followed by an immediate read from the configuration register . . . . . 25 figure 13. configuration register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. t os and t hys write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. temperature variation vs. voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. so8 ? 8-lead plastic small outline package mechanical drawing . . . . . . . . . . . . . . . . . . . . 33 figure 18. msop8 (tssop8) ? 8-lead, thin shrink small outline (3 mm x 3 mm) package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. carrier tape for so8 and msop8 (tssop8) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 21. device topside marking information (so8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22. device topside marking information (msop8/tssop8). . . . . . . . . . . . . . . . . . . . . . . . . . . 38
description stlm75 6/40 doc id 13296 rev 12 1 description the stlm75 is a high-precision digital cmos temperature sensor ic with a sigma-delta temperature-to-digital converter and an i 2 c-compatible serial digital interface. it is targeted for general applications such as personal computers, system thermal management, electronics equipment, and industrial controllers, and is packaged in the industry standard 8-lead tssop and so8 packages. the device contains a band gap temperatur e sensor and 9-bit adc which monitor and digitize the temperature to a resolution up to 0.5 c. the stlm75 is typically accurate to (3 c - max) over the full temperature measurement range of ?55 c to 125 c with 2 c accuracy in the ?25 c to +100 c range. the stlm75 is pin-for-pin and software compatible with the lm75b. the stlm75 is specified for operating at supply voltages from 2.7 v to 5.5 v. operating at 3.3 v, the supply current is typically (125 a). the on-board sigma-delta analog-to-digital converter (adc) converts the measured temperature to a digital value that is calibrated in degrees centigrade; for fahrenheit applications a lookup table or conversion routine is required. the stlm75 is factory-calibrated and requires no external components to measure temperature. 1.1 serial communications the stlm75 has a simple 2-wire i 2 c-compatible digital serial interface which allows the user to access the data in the temperature register at any time. it communicates via the serial interface with a master controller which operates at speeds up to 400 khz. three pins (a0, a1, and a2) are available for address selection, and enable the user to connect up to 8 devices on the same bus without address conflict. in addition, the serial interface gives the user easy access to all stlm75 registers to customize operation of the device.
stlm75 description doc id 13296 rev 12 7/40 1.2 temperature sensor output the stlm75 temperature sensor has a dedicated open drain overlimit signal/interrupt (os /int) output which features a thermal alarm function. this function provides a user- programmable trip and turn-off temperature. it can operate in either of two selectable modes: comparator mode , and interrupt mode . at power-up the stlm75 immediately begins measuring the temperature and converting the temperature to a digital value. the measured temperature value is compared with a temperature limit (which is stored in the 16-bit (t os ) read/write register), and the hysteres is temperature (which is stored in the 16-bit (t hys ) read/write register). if the measured value exceeds these limits, the os /int pin is activated (see figure 3 on page 8 and table 2 on page 14 ). note: see pin descriptions on page 9 for details. figure 1. logic diagram 1. sda and os /int are open drain. ai11 8 99 s da (1) v dd s tlm75 gnd s cl o s /int (1) a 0 a 1 a 2
description stlm75 8/40 doc id 13296 rev 12 figure 2. connections (so8 and msop8/tssop8) 1. sda and os /int are open drain. figure 3. functional block diagram table 1. signal names pin sym type/direction description 1sda (1) 1. sda and os /int are open drain. input/output serial data input/output 2 scl input serial clock input 3os /int (1) output overlimit signal/interrupt alert output 4 gnd supply ground ground 5a 2 input address2 input 6a 1 input address1 input 7a 0 input address0 input 8v dd supply power supply voltage (2.7 v to 5.5 v) 1 a 2 gnd a 1 a 0 scl sda (1) v dd os/int (1) ai11841 2 3 4 8 7 6 5 ai11833a temperature sensor and analog-to-digital converter (adc) - a 1 a 0 v dd a 2 gnd configuration register sda scl os/int 2-wire i 2 c interface pointer register control and logic comparator temperature register thys set point register tos set point register
stlm75 description doc id 13296 rev 12 9/40 1.3 pin descriptions see figure 1 on page 7 and table 1 on page 8 for a brief overview of the signals connected to this device. 1.3.1 sda (open drain) this is the serial data input/output pin for the 2-wire serial communication port. 1.3.2 scl this is the serial clock input pin for the 2-wire serial communication port. 1.3.3 os /int (open drain) this is the overlimit signal/interrupt alert outp ut pin. it is open drain, so it needs a pull-up resistor. in interrupt mode, it outputs a pulse whenever the measured temperature exceeds the programmed threshold (t os ). it behaves as a thermostat, toggling to indicate whether the measured temperature is above or below the threshold and hysteresis (t hys ). 1.3.4 gnd ground; it is the reference for the power supply. it must be connected to system ground. 1.3.5 a2, a1, a0 a2, a1, and a0 are selectable address pins for the 3 lsbs of the i 2 c interface address. they can be set to v dd or gnd to provide 8 unique address selections. 1.3.6 v dd this is the supply voltage pin, and ranges from +2.7 v to +5.5 v.
operation stlm75 10/40 doc id 13296 rev 12 2 operation after each temperature measurement and analog-to-digital conversion, the stlm75 stores the temperature as a 16-bit two?s complement number (see table 5: register pointers selection summary on page 17 ) in the 2-byte temperature register (see table 7 on page 18 ). the most significant bit (s) indicates if the temperature is positive or negative: for positive numbers s = 0, and for negative numbers s = 1. the most recently converted digital measurement can be read from the temperature register at any time. since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress. the temperature data is provided by the 9 msbs (bits 15 through 7). bits 6 through 0 are unused. table 3 on page 15 gives examples of the digital output data and corresponding temperatures. the data is compared to the values in the t os and t hys registers, and then the os is updated based on the result of the comparison and the operating mode. the alarm fault tolerance is controlled by the ft 1 and ft0 bits in the configuration register. they are used to set up a fault queue. this prevents false tripping of the os /int pin when the stlm75 is used in a noisy environment (see table 3 on page 15 ). the active state of the os output can be changed via the polarity bit (pol) in the configuration register. the power-up default is active-low. if the user does not wish to use the ther mostat capabilities of the stlm75, the os output should be left floating. note: if the thermostat is not used, the t os and t hys registers can be used for general storage of system data.
stlm75 operation doc id 13296 rev 12 11/40 2.1 applications information stlm75 digital temperature sensors are optimal for thermal management and thermal protection applications. they require no external components for operations except for pull- up resistors on scl, sda, and os /int outputs. a 0.1 f bypass capacitor on v dd is recommended. the sensing device of stlm75 is the chip itself. the typical interface connection for this type of digital sensor is shown in figure 4 on page 11 . intended applications include: system thermal management computers/disk drivers electronics/test equipment power supply modules consumer products battery management fax/printers management automotive figure 4. typical 2-wire interface connections diagram 1. sda and os /int are open drain. ai12200 pull-up v dd o.s./int (1) v dd v dd master device 0.1 f stlm75 scl gnd sda (1) pull-up v dd 10k 10k 10k a 0 a 1 a 2 i 2 c address = 1001000 (1001a 2 a 1 a 0 )
operation stlm75 12/40 doc id 13296 rev 12 2.2 thermal alarm function the stlm75 thermal alarm function provides user-programmable ther mostat capability and allows the stlm75 to function as a standalone thermostat without using the serial interface. the os output is the alarm output. this signal is an open drain output, and at power-up, this pin is configured with active-low polarity by default. 2.3 comparator mode in comparator mode, each time a temperature-to-digital (t-to-d) conversion occurs, the new digital temperature is compared to the value stored in the t os and t hys registers. if a fault tolerance number of consecutive temperature measurements are greater than the value stored in the t os register, the os output will be asserted. for example, if the ft1 and ft0 bits are equal to ?10? (fault tolerance = 4), four consecutive temperature measurements must exceed t os to activate the os output. once the os output is active, it will remain active until the first time the meas ured temper ature drops below the temperature stored in the t hys register. when the thermostat is in comparator mode, the os can be programmed to operate with any amount of hysteresis. the os output becomes active when the measured temperature exceeds the t os value a consecutive number of times as defined by the ft1 and ft0 fault tolerance (ft) bits in the configuration register. the os then becomes inactive when the temperature falls below the value stored in t hys register for a consecutive number of times as defined by the fault tolerance bits (ft1 and ft0). putting the device into shutdown mode does not clear os in comparator mode.
stlm75 operation doc id 13296 rev 12 13/40 2.4 interrupt mode in interrupt mode, the os output first becomes active when the measured temperature exceeds the t os value a consecutive number of times as determined by the ft value in the configuration register. once activated, the os can only be cleared by either putting the stlm75 into shutdown mode or by reading from any register (temperature, configuration, t os , or t hys ) on the device. once the os has been deactivated, it will only be reactivated when the measured temperature falls below the t hys value a consecutive number of times equal to the ft value. figure 5 illustrates typical os output temperature response. note: the os can only be cleared by putting the device into shutdown mode or reading any register. thus, this interrupt/clear process is cyclical between the t os and t hys events (i.e., t os , clear, t hys , clear, t os , clear, t hys , clear, and so forth). these interrupt mode resets of the os /int pin occur only when the stlm75 is read or placed into shutdown mode. otherwise, os /int would remain active independently for any event. figure 5. os output temperature response diagram 1. these interrupt mode resets of o.s. occur only when stlm75 is read or placed in shutdown. otherwise, o.s. would remain active indefinitely for any event.
operation stlm75 14/40 doc id 13296 rev 12 2.5 fault tolerance for both comparator and interrupt modes, the alarm ?fault tolerance? setting plays a role in determining when the os output will be activated. fault to lerance refers to the number of consecutive times an error condition must be detected before the user is notified. higher fault tolerance settings can help eliminate fals e alarms caused by noise in the system. the alarm fault tolerance is controlled by the bits (4 and 3) in the configuration register. these bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in ta bl e 2 . at power-up, these bits both default to logic '0'. note: os output will be asserted one t conv after fault tolerance is met, provided that the error condition remains. 2.6 shutdown mode for power-sensitive applications, the stlm75 offers a low-power shutdown mode. the sd bit in the configuration register controls shutdown mode. when sd is changed to logic '1,' the conversion in progress will be completed and the result stored in the temperature register, after which the stlm75 will go in to a low-power standby state. the os output will be cleared if the thermostat is operating in interrupt mode and the os will remain unchanged in comparator mode. the 2-wire interface remains operational in shutdown mode, and writing a '0' to the sd bit returns the stlm75 to normal operation. table 2. fault tolerance setting ft1 ft0 stlm75 (consecutive faults) comments 0 0 1 power-up default 01 2 10 4 11 6
stlm75 operation doc id 13296 rev 12 15/40 2.7 temperature data format ta bl e 3 shows the relationship between the output digital data and the external temperature. temperature data for the temperature, t os , and t hys registers is represented as a 9-bit, two?s complement word. the left-most bit in the output data stream contains temperature polarity information for each conversion. if the sign bit is '0', the temperature is positive and if the sign bit is '1,' the temperature is negative. 2.8 bus timeout feature the stlm75 supports an smbus compatible ti meout function which will reset the serial i 2 c/smbus interface if sda is held low for a period greater than the timeout duration between a start and stop condition. if this occurs, the device will release the bus and wait for another start condition. table 3. relationship between temperature and digital output temperature digital output binary hex +125 c 0 1111 1010 0fah +25 c 0 0011 0010 032h +0.5 c 0 0000 0001 001h 0 c 0 0000 0000 000h ?0.5 c 1 1111 1111 1ffh ?25 c 1 1100 1110 1ceh ?40 c 1 1011 0000 1b0h ?55 c 1 1001 0010 192h
functional description stlm75 16/40 doc id 13296 rev 12 3 functional description the stlm75 registers have unique pointer designations which are defined in ta b l e 5 o n page 17 . whenever any read/write operation to the stlm75 register is desired, the user must ?point? to the device register to be accessed. all of these user-accessible registers can be accessed via the digital serial interface at anytime (see serial interface on page 20 ), and they include: command register/address pointer register configuration register temperature register overlimit signal temperature register (t os ) hysteresis temperature register (t hys ) 3.1 registers and register set formats 3.1.1 command/pointer register the most significant bits (msbs) of the command register must always be zero. writing a '1' into any of these bits will caus e the current operation to be te rminated (bit 2 through bit 7 must be kept '0', see ta bl e 4 ). the command register retains pointer information between operations (see ta b l e 5 ). therefore, this register only needs to be up dated once for consecutive read operations from the same register. all bits in the command register default to '0' at power-up. table 4. command/pointer register format msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000p1p0 pointer/register select bits
stlm75 functional description doc id 13296 rev 12 17/40 3.1.2 configuration register the configuration register is used to store the device settings such as device operation mode, os operation mode, os polarity, and os fault queue. the configuration register allows the user to program various options such as thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. the user has read/write access to all of the bits in the configuration register except the msb (bit7), which is reserved as a ?read only? bit (see ta b l e 6 ). the entire register is volatile and thus powers-up in its default state only. table 5. register pointers selection summary pointer value (h) p1 p0 name description width (bits) type (r/w) power-on default comments 00 0 0 temp temperature register 16 read- only n/a to store measured temperature data 01 0 1 conf configuration register 8r/w 00 02 1 0 t hys hysteresis register 16 r/w 4b00 default = 75 c 03 1 1 t os overtemperature shutdown 16 r/w 5000 set point for overtemperature shutdown (t os ) limit default = 80 c table 6. configuration register format byte msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stlm75 reserved 0 0 ft1 ft0 pol m sd default00000000 keys: sd = shutdown control bit ft1 = fault tolerance1 bit m = thermostat mode (1) bit 5 = must be set to '0'. pol = output polarity (2) bit 6 = must be set to '0'. ft0 = fault tolerance0 bit bit 7 = must be set to '0'. reserved. 1. indicates operation mode; 0 = comparator mode, and 1 = interrupt mode (see comparator mode and interrupt mode on page 13 ). 2. the os is active-low ('0').
functional description stlm75 18/40 doc id 13296 rev 12 3.1.3 temperature register the temperature register is a two-byte (16-bit) ?read only? register (see table 7 on page 18 ). digital temperatures from the t-to-d converter are stored in the temperature register in two?s complement format, and the contents of this register are updated each time the t-to-d conversion is finished. the user can read data from the temperature register at any time. when a t-to-d conversion is completed, the new data is loaded into a comparator buffer to evaluate fault conditions and will update the temperature regist er if a read cycle is not ongoing. if a read is ongoing, the previous temperature will be read. accessing the st lm75 continuously without waiting at least one conversion time between co mmunications will prevent the device from updating the temperature register with a new temperature conversion result. consequently, the stlm75 should not be accessed continuously with a wait time of less than t conv (max). all unused bits following the digital temper ature will be zero. the msb position of the temperature register always contains the sign bit for the digital temperature, and bit14 contains the temperature msb. all bits in the temperature register default to zero at power- up. note: these are comparable formats to the lm75. 3.1.4 overlimit temp erature register (t os ) the t os register is a two-byte (16-bit) read/write register that stores the user- programmable upper trip-point temperature for the thermal alarm in two?s complement format (see table 8 on page 19 ). this register defaults to 80 c at power-up (i.e., 0101 0000 0000 0000). the format of the t os register is identical to that of the temperature register. the msb position contains the sign bit for the digital temperature and bit14 contains the temperature msb. for 9-bit conversions, the trip-point temperature is defined by the 9 msbs of the t os register, and all remaining bits are ?don?t cares?. table 7. temperature register format bytes hs byte ls byte bits msb tmsb tlsb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stlm75 td8 (sign) td7 (tmsb) td 6 td 5 td 4 td 3 td 2 td 1 td0 (tlsb) 000000 0 keys: sb = two?s complement sign bit tmsb = temperature msb tlsb = temperature lsb tdx = temperature data bits
stlm75 functional description doc id 13296 rev 12 19/40 3.1.5 hysteresis temperature register (t hys ) t hys register is a two-byte (16-bit) read/write register that stores the user- programmable lower trip-point temperature for the thermal alarm in two?s complement format (see ta b l e 8 ). this register defaults to 75 c at power-up (i.e., 0100 1011 0000 0000). the format of this register is the same as that of the temperature register. the msb position contains the sign bit for the digital temper ature and bit14 contains the temperature msb. note: these are comparable formats to the ds75 and lm75. 3.2 power-up default conditions the stlm75 always powers up in the following default states: thermostat mode = comparator mode polarity = active-low fault tolerance = 1 fault (i.e., relevant bits set to '0' in the configuration register) t os = 80 c t hys = 75 c register pointer = 00 (temperature register) note: after power-up these conditions can be reprogrammed via the serial interface. table 8. t os and t hys register format bytes hs byte ls byte bits msb tmsb tlsb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stlm75 sb tmsb td td td td td td 9-bit tlsb 000000 0 keys: sb = two?s complement sign bit tmsb = temperature msb tlsb = temperature lsb td = temperature data
functional description stlm75 20/40 doc id 13296 rev 12 3.3 serial interface writing to and reading from the stlm75 registers is accomplished via the two-wire serial interface protocol which requires that one devi ce on the bus initiates and controls all read and write operations. this device is called th e ?master? device. the master device also generates the scl signal which provides the clock signal for all other devices on the bus. these other devices on the bus are called ?sla ve? devices. the stlm75 is a slave device (see ta b l e 9 ). both the master and slave devices can send and receive data on the bus. during operations, one data bit is transmitted per clock cycle. all operations follow a repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note: there are no unused clock cycles during any operation, so there must not be any breaks in the data stream and acks/nacks during data transfers. consequently, having too few clock cycles can lead to incorrect operation if an inadvertent 8-bit read from a 16-bit register occurs. so, the entire word must be transferred out regardless of the superflous trailing zeroes. 3.4 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock lin e is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined (see figure 6 on page 21 ): 3.4.1 bus not busy both data and clock lines remain high. 3.4.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 3.4.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. table 9. stlm75 serial bus slave addresses msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 0 1 a2 a1 a0 r/w
stlm75 functional description doc id 13296 rev 12 21/40 3.4.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. th e device that controls the message is called ?master?. the devices that are controlled by the master are called ?slaves?. figure 6. serial bus data transfer sequence ai005 8 7 data clock data line s table data valid s ta rt condition change of data allowed s top condition
functional description stlm75 22/40 doc id 13296 rev 12 3.4.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse (see figure 7 ). a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 7. acknowledgement sequence ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
stlm75 functional description doc id 13296 rev 12 23/40 3.5 read mode in this mode the master reads the stlm75 slave after setting the slave address (see figure 8 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. there are two read modes: preset pointer locations (e.g. temperature, t os and t hys registers), and pointer setting (the pointer has to be set for the register that is to be read) note: the temperature register pointer is usually the default pointer. these modes are shown in the read mo de typical timing diagrams (see figure 9 , figure 10 , and figure 11 ). figure 8. slave address location ai12226 r/w slave address start a 0 1 a2 a1 a0 10 msb lsb
functional description stlm75 24/40 doc id 13296 rev 12 figure 9. typical 2-byte read from preset pointer location (e.g. temp - t os , t hys ) figure 10. typical pointer set followed by an immediate read for 2-byte register (e.g. temp) figure 11. typical 1-byte read from the configuration register with preset pointer ai12227 11 91 99 1 start by master address byte most significant data byte least significant data byte ack by stlm75 ack by master no ack by master stop cond. by master 0 0 1 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ai12228 11 91 99 1 repeat start by master address byte most significant data byte least significant data byte ack by stlm75 ack by master no ack by master stop cond. by master 0 0 1 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 11 99 1 start by master address byte pointer byte ack by stlm75 ack by stlm75 0 0 1 a2 a1 a0 r/w 0 0 0 0 0 0 d1 d0 11 99 1 start by master address byte data byte ack by stlm75 no ack by master stop cond. by master 0 0 1 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 ai12229
stlm75 functional description doc id 13296 rev 12 25/40 3.6 write mode in this mode the master transmitter transmits to the stlm75 slave receiver. bus protocol is shown in figure 12 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addr essed device that word address will follow and is to be written to the on-chip address pointer. these modes are shown in the write mo de typical timing diagrams (see figure 12 , and figure 13 , and figure 14 ). figure 12. typical pointer set followed by an immediate read from the configuration register figure 13. configuration register write ai12230 1919 repeat start by master ack by stlm75 no ack by stlm75 stop cond. by master 1 0 0 1 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w address byte data byte 11 99 1 start by master address byte pointer byte ack by stlm75 ack by stlm75 0 0 1 a2 a1 a0 r/w 0 0 0 0 0 0 d1 d0 ai12231 11 9919 1 start by master address byte pointer byte ack by stlm75 ack by stlm75 ack by stlm75 stop cond. by master 0 0 1 a2 a1 a0 r/w 0 0 0 0 0 0 0 0 0 d4 d3 d2 d1 d0 d1 d0 configuration byte
functional description stlm75 26/40 doc id 13296 rev 12 figure 14. t os and t hys write ai12232 1919 ack by stlm75 ack by stlm75 stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 most significant data byte least significant data byte 11 99 1 start by master address byte pointer byte ack by stlm75 ack by stlm75 0 0 1 a2 a1 a0 r/w 0 0 0 0 0 0 d1 d0
stlm75 typical operating characteristics doc id 13296 rev 12 27/40 4 typical operating characteristics figure 15. temperature variation vs. voltage ?60 ?40 ?20 0 20 40 60 80 100 120 140 23456 ?20 0.5 85 110 voltage (v) temperature ( c) 125 ai12258
maximum ratings stlm75 28/40 doc id 13296 rev 12 5 maximum ratings stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 10. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off, v bat off) ?60 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage v cc +0.5 v v dd supply voltage 7.0 v v out output voltage v dd + 0.5 v i o output current 10 ma p d power dissipation 320 mw ja thermal resistance so8 128.4 c/w msop8 (tssop8) 216.3 c/w 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds.
stlm75 dc and ac parameters doc id 13296 rev 12 29/40 6 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e 1 1 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 11. operating and ac measurement conditions parameter conditions unit v dd supply voltage 2.7 to 5.5 v ambient operating temperature (t a ) ?55 to 125 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v cc v input and output timing reference voltages 0.3 to 0.7v cc v
dc and ac parameters stlm75 30/40 doc id 13296 rev 12 table 12. dc and ac characteristics sym description test condition (1) 1. valid for ambient operating temperature: t a = ?55 to 125 c; v dd = 2.7 v to 5.5 v (except where noted). min typ (2) 2. typical number taken at v dd = 3.0 v, t a = 25 c max unit v dd supply voltage t a = ?55 to +125 c 2.7 5.5 v i dd v dd supply current, active temperature conversions v dd = 3.3 v 125 150 a v dd supply current, communication only t a = 25 c 70 100 a i dd1 shutdown mode supply current, serial port inactive t a = 25 c 1.0 a accuracy for corresponding range 2.7 v v dd 5.5 v ?25 c < t a < 100 0.5 2.0 c ?55 c < t a < 125 0.5 3.0 c resolution 9-bit temperature data 0.5 c/lsb 9bits t conv conversion time 9 150 ms t os overtemperature shutdown default value 80 c t hys hysteresis default value 75 c v ol1 os saturation voltage (v dd = 5v) 4 ma sink current 0.5 v v ih input logic high digital pins (scl, sda, a2-a0) 0.7 x v dd v dd + 0.5 v v il input logic low digital pins ?0.45 0.3 x v dd v v ol2 output logic low (sda) i ol2 = 3 ma 0.4 v cin capacitance 5 pf
stlm75 dc and ac parameters doc id 13296 rev 12 31/40 figure 16. bus timing requirements sequence table 13. ac characteristics sym parameter (1)(2) 1. valid for ambient operating temperature: t a = ?55 to 125 c; v dd = 2.7 v to 5.5 v (except where noted). 2. devices are tested at maximum clock frequency of 400 khz. min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t f sda and scl fall time 300 ns t hd:dat (3) 3. transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of scl. data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns t time-out sda time low for reset of serial interface (4) 4. for smbus compatibility, the stlm75 supports bus ti me-out. holding the sda line low for a time greater than time-out will cause the stlm75 to reset the sda to the idle state of serial bus communication (sda set to high). 75 325 ms ai005 8 9 s da p t s u: s to t s u: s ta thd: s ta s r s cl t s u:dat tf thd:dat tr thigh tlow thd: s ta tbuf s p
package mechanical data stlm75 32/40 doc id 13296 rev 12 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stlm75 package mechanical data doc id 13296 rev 12 33/40 figure 17. so8 ? 8-lead plastic small outline package mechanical drawing note: drawing is not to scale. s o-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane table 14. so8 ? 8-lead plastic small outline package mechanical data sym mm inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27 0.050 h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 0.127 0.016 0.050 l1 1.04 0.041
package mechanical data stlm75 34/40 doc id 13296 rev 12 figure 18. msop8 (tssop8) ? 8-lead, thin shrink small outline (3 mm x 3 mm) package mechanical drawing note: drawing is not to scale. e 3 _me 1 8 ccc c l e e1 d a2 a k e b 4 5 a1 l1 l2 table 15. msop8 (tssop8) ? 8-lead, thin shrink small outline (3 mm x 3 mm) package mechanical data sym mm inches typ min max typ min max a1.100.043 a1 0.00 0.15 0.000 0.006 a2 0.85 0.75 0.95 0.034 0.030 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 d 3.00 2.80 3.20 0.118 0.110 0.126 e 4.90 4.65 5.15 0.193 0.183 0.203 e1 3.00 2.80 3.10 0.118 0.110 0.122 e0.65 0.026 l 0.60 0.40 0.80 0.024 0.016 0.032 l1 0.95 0.037 l2 0.25 0.010 k 08 08 ccc 0.10 0.004
stlm75 package mechanical data doc id 13296 rev 12 35/40 figure 19. carrier tape for so8 and msop8 (tssop8) packages t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 16. carrier tape dimensions for so8 and msop8 (tssop8) packages package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty so8 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 6.50 0.10 5.30 0.10 2.20 0.10 8.00 0.10 0.30 0.05 mm 2500 msop8 (tssop8) 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 5.30 0.10 3.40 0.10 1.40 0.10 8.00 0.10 0.30 0.05 mm 1000
package mechanical data stlm75 36/40 doc id 13296 rev 12 figure 20. reel schematic note: the dimensions given in ta b l e 1 7 incorporate tolerances that cover all variations on critical parameters a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 17. reel dimensions for 12 mm carrier tape - so8 and msop8 (tssop8) packages package a (max) b (min) c d (min) n (min) g t (max) so8 330 mm (13-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm msop8 (tssop8) 180 mm (7-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 12.4 mm + 2/?0 mm 18.4 mm
stlm75 part numbering doc id 13296 rev 12 37/40 8 part numbering table 18. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stlm75 m 2 f device type stlm75 package m = so8 ds = msop8 (tssop8) temperature range 2 = ?55 to 125 c shipping method f = ecopack ? package, tape & reel e = ecopack ? package, tube
package marking information stlm75 38/40 doc id 13296 rev 12 9 package marking information figure 21. device topside marking information (so8) 1. traceability codes figure 22. device topside marking information (msop8/tssop8) 1. traceability codes xxxxx (1) stlm75m2 am04934v1 lm75 xxxx (1) am04935v1
stlm75 revision history doc id 13296 rev 12 39/40 10 revision history table 19. document revision history date revision changes 23-dec-2005 1 initial release. 24-feb-2006 2 updated template, characteristics (figure 1 , 2 , 3 , 4 , 5 , ; table 1 , 6 , 8 , 11 , 12 , 13 ) 06-mar-2006 3 updated characteristics (figure 5 ; table 11 , 12 , 13 ) 28-jul-2006 4 updated figure 1 and 5 22-jan-2007 5 updated features (cover page), dc and ac characteristics ( ta b l e 1 2 ), package mechanical data ( figure 17 , figure 14 , figure 18 , ta b l e 1 5 ) and part numbering ( ta b l e 1 8 ). 01-mar-2007 6 updated cover page (package information); section 2.3: comparator mode ; ta bl e 1 2 ; package mechanical data ( figure 18 , and ta bl e 1 5 ); and part numbering ( ta b l e 1 8 ). 06-jun-2007 7 updated cover page, document status upgraded to full datasheet, updated ta bl e 1 3 . 07-jul-2008 8 minor text changes; added section 2.8: bus timeout feature ; updated section 3.1.3: temperature register . 18-jul-2008 9 updated cover page and ta bl e 1 8 . 09-apr-2009 10 updated features , ta bl e 1 0 , 12 , 13 , text in section 7: package mechanical data ; added tape and reel information figure 19 , ta bl e 1 6 ; minor reformatting. 24-mar-2010 11 updated section 2.3 , section 2.5 ; footnote 1 of ta b l e 1 0 ; reformatted document. 17-aug-2010 12 updated ta bl e 1 6 ; added figure 20 , ta b l e 1 7 , section 9: package marking information ; minor textual changes.
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